Fe2O3.net DokuWiki https://wiki.fe2o3.net/ 2026-04-18T07:09:45-0400 Fe2O3.net DokuWiki https://wiki.fe2o3.net/ https://wiki.fe2o3.net/lib/tpl/dokuwiki/images/favicon.ico text/html 2018-09-09T15:16:13-0400 gtfjt (gtfjt@undisclosed.example.com) wiki:nightowl:addressing https://wiki.fe2o3.net/doku.php?id=wiki:nightowl:addressing&rev=1536520573&do=diff AddressPort SizeSignalDescription11xx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx32kseg2 1023MBKernel cached tasks10xx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx32kuseg 1024MB01xx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx32kuseg 1024MB001x:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxxN/A text/html 2018-08-17T13:15:34-0400 gtfjt (gtfjt@undisclosed.example.com) wiki:nightowl:uart https://wiki.fe2o3.net/doku.php?id=wiki:nightowl:uart&rev=1534526134&do=diff 2681 UART Interfacing Reads * A0-A3 must be metastable for 10ns prior to assertion of RDN/WRN. * A0-A3 must remain metastable for 100ns after assertion of RDN/WRN. * CEN may be concurrent with RDN/WRN assertion. Writes * D0-D7 are latched on WRN↑. WRN ⇐ /Wr text/html 2018-08-17T11:28:48-0400 gtfjt (gtfjt@undisclosed.example.com) wiki:nightowl https://wiki.fe2o3.net/doku.php?id=wiki:nightowl&rev=1534519728&do=diff Nightowl RISC * Clock generation and reset * Bus operation * Address space decoding and device select generation * UART interfacing text/html 2018-08-10T23:06:10-0400 gtfjt (gtfjt@undisclosed.example.com) wiki:nightowl:buscycle https://wiki.fe2o3.net/doku.php?id=wiki:nightowl:buscycle&rev=1533956770&do=diff R3041 Bus Operation * Host asserts ALE to indicate stable address on muxed AD31:AD0 lines. * Bus logic enables shift register count of PhiClk for wait-state generation. * Device generates latched select from decoded address. * Device asserts /RdCEn and /Ack from its selected PhiClk wait-state line. text/html 2018-08-09T11:48:19-0400 gtfjt (gtfjt@undisclosed.example.com) wiki:nightowl:clockreset - created https://wiki.fe2o3.net/doku.php?id=wiki:nightowl:clockreset&rev=1533829699&do=diff The datasheet claims 2x input clocking down to 4MHz. ---------- PhiClk is specified in documentation, but the precise relationship to /SysClk is not given. Let's say PhiClk trails /SysClk by about 90 degrees. We get this by clocking /SysClk (D) into a flip-flop on the trailing edge of Clk2xIn (Clk).