wiki:nightowl:clockreset
The datasheet claims 2x input clocking down to 4MHz.
PhiClk is specified in documentation, but the precise relationship to /SysClk is not given. Let's say PhiClk trails /SysClk by about 90 degrees. We get this by clocking /SysClk (D) into a flip-flop on the trailing edge of Clk2xIn (Clk).
wiki/nightowl/clockreset.txt · Last modified: 2018/08/09 11:48 by gtfjt
