1. Host asserts ALE to indicate stable address on muxed AD31:AD0 lines.
2. Bus logic enables shift register count of PhiClk for wait-state generation.
3. Device generates latched select from decoded address.
4. Device asserts /RdCEn and /Ack from its selected PhiClk wait-state line.
5. Host asserts /DataEn to indicate that the bus is tri-stated and ready for device data. This may occur before or after /Ack.
6. Device presents data to the bus, output gated by /DataEn after /Ack.
7. Host deasserts /Last to indicate end of bus transaction.
8. Bus logic resets the wait state counter, latched enables, etc.

Notes:

1. Assert /ACK once per bus transaction for both reads and writes after data address selection is complete.
2. Assert /RdCEn once per data word in read burst. First assertion of /RdCEn is coincident with /Ack. Subsequent assertions of /RdCEn are timed using a (usually) shorter wait-state count than the initial access.

• DSA = DSB ⇐ ALE ∥ FB
• CP ⇐ !/SysClk
• /MR ⇐ !(/Rd & /Wr)
• /BusErr ⇐ !Q7