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R3041 Bus Operation

Host asserts ALE to indicate stable address on muxed AD31:AD0 lines.
Bus logic enables shift register count of PhiClk for wait-state generation.
Device generates latched select from decoded address.
Device asserts /RdCEn and /Ack from its selected PhiClk wait-state line.
Host asserts /DataEn to indicate that the bus is tri-stated and ready for device data. This may occur before or after /Ack.
Device presents data to the bus, output gated by /DataEn after /Ack.
Host deasserts /Last to indicate end of bus transaction.

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