====== R3041 Bus Operation ======

  - Host asserts ALE to indicate stable address on muxed AD31:AD0 lines.
  - Bus logic enables shift register count of PhiClk for wait-state generation.
  - Device generates latched select from decoded address.
  - Device asserts /RdCEn and /Ack from its selected PhiClk wait-state line.
  - Host asserts /DataEn to indicate that the bus is tri-stated and ready for device data. This may occur before or after /Ack.
  - Device presents data to the bus, output gated by /DataEn after /Ack.
  - Host deasserts /Last to indicate end of bus transaction.
  - Bus logic resets the wait state counter, latched enables, etc.

Notes:

  - Assert /ACK once per bus transaction for both reads and writes after data address selection is complete.
  - Assert /RdCEn once per data word in read burst. First assertion of /RdCEn is coincident with /Ack. Subsequent assertions of /RdCEn are timed using a (usually) shorter wait-state count than the initial access.

===== Wait-State Generation =====

  * DSA = DSB ⇐ ALE ∥ FB
  * CP ⇐ !/SysClk
  * /MR ⇐ !(/Rd & /Wr)
  * /BusErr ⇐ !Q7