^Address^Port Size^Signal^Description^
|''11xx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx''|32|kseg2 1023MB|Kernel cached tasks|
|''10xx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx''|32|kuseg 1024MB||
|''01xx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx''|32|kuseg 1024MB||
|''001x:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx''|N/A||Inaccessible 512MB|
|''0001:1111:11xx:xxxx:xxxx:xxxx:xxxx:xxxx''|8||Kernel Boot and I/O|
|''0001:1111:1100:0xxx:xxxx:xxxx:xxxx:xxxx''|8|/ROMSEL|Boot ROM up to 512K|
|''0001:1111:1111:1xxx:xxxx:xxxx:xxxx:xxxx''|8|||
|''0001:1111:1111:1111:1111:1111:1111:xxxx''|8|/REGSEL|Onboard I/O port registers|
|''0001:1111:1111:1111:1111:1111:1110:xxxx''|8|/SCCSEL|Philips 2681+ DUART|
|''0001:10xx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx''|8|/IO8SEL|8-bit I/O space|
|''0001:01xx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx''|16|/IO16SEL|16-bit I/O space|
|''0001:00xx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx''|32||32-bit I/O space|
|''0000:11xx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx''|32||64MB Remap Window|
|''0000:10xx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx''|32||
|''0000:01xx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx''|32||
|''0000:00xx:xxxx:xxxx:xxxx:xxxx:xxxx:xxxx''|32|/RAMSEL|SRAM 64MB starting at 0x00000000|

====== GAL Address Decoding and Select Line Generation ======

  * The master address decoder (MAD) shall be implemented in a 22V10 programmable logic device.
  * Select line outputs are configured as inverting so they will go high on asynchronous reset.
  * Address lines are not yet metastable on ALE↑. Decoding logic may proceed ungated, with select output flip-flops clocked on next SysClk↓ following ALE↑.
  * One FF feeds back to enable all select line outputs.
  * /Last high input while /OE enable is low provides the internal asynchronous preset.
  * A31:A26 are fully decoded to match 64MB regions.

  * /ROMSEL ⇐ /A31 & /A30 & /A29 & A28 & A27 & A26
  * /SCSEL ⇐ 
  * /RAMSEL ⇐ /A31 & /A30 & /A29 & A28 & A27 & A26
  *