wiki:nightowl:clockreset
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wiki:nightowl:clockreset [2018/08/09 11:48] (current) gtfjt created |
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| + | The datasheet claims 2x input clocking down to 4MHz. | ||
| + | ---- | ||
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| + | PhiClk is specified in documentation, but the precise relationship to /SysClk is not given. Let's say PhiClk trails /SysClk by about 90 degrees. We get this by clocking /SysClk (D) into a flip-flop on the trailing edge of Clk2xIn (Clk). | ||
wiki/nightowl/clockreset.txt ยท Last modified: 2018/08/09 11:48 by gtfjt
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