wiki:nightowl:buscycle
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wiki:nightowl:buscycle [2018/08/09 15:14] gtfjt |
wiki:nightowl:buscycle [2018/08/10 23:06] (current) gtfjt |
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| Notes: | Notes: | ||
| - | - Assert /ACK once per bus transaction after data address selection is complete for both reads and writes. | + | - Assert /ACK once per bus transaction for both reads and writes after data address selection is complete. |
| - Assert /RdCEn once per data word in read burst. First assertion of /RdCEn is coincident with /Ack. Subsequent assertions of /RdCEn are timed using a (usually) shorter wait-state count than the initial access. | - Assert /RdCEn once per data word in read burst. First assertion of /RdCEn is coincident with /Ack. Subsequent assertions of /RdCEn are timed using a (usually) shorter wait-state count than the initial access. | ||
| + | |||
| + | ===== Wait-State Generation ===== | ||
| + | |||
| + | * DSA = DSB ⇐ ALE ∥ FB | ||
| + | * CP ⇐ !/SysClk | ||
| + | * /MR ⇐ !(/Rd & /Wr) | ||
| + | * /BusErr ⇐ !Q7 | ||
| + | |||
wiki/nightowl/buscycle.1533842041.txt.gz · Last modified: 2018/08/09 15:14 by gtfjt
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