wiki:nightowl:buscycle
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wiki:nightowl:buscycle [2018/08/09 13:43] gtfjt created |
wiki:nightowl:buscycle [2018/08/10 23:06] (current) gtfjt |
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| ====== R3041 Bus Operation ====== | ====== R3041 Bus Operation ====== | ||
| - | - Host asserts ALE ⇒ Address on muxed AD31:AD0 lines is decoded and latched select is generated. | + | - Host asserts ALE to indicate stable address on muxed AD31:AD0 lines. |
| - | - Device asserts /RdCEn and /Ack on PhiClk↓ | + | - Bus logic enables shift register count of PhiClk for wait-state generation. |
| - | - Host asserts /DataEn as data output enable (/OE) to device. | + | - Device generates latched select from decoded address. |
| + | - Device asserts /RdCEn and /Ack from its selected PhiClk wait-state line. | ||
| + | - Host asserts /DataEn to indicate that the bus is tri-stated and ready for device data. This may occur before or after /Ack. | ||
| + | - Device presents data to the bus, output gated by /DataEn after /Ack. | ||
| - Host deasserts /Last to indicate end of bus transaction. | - Host deasserts /Last to indicate end of bus transaction. | ||
| + | - Bus logic resets the wait state counter, latched enables, etc. | ||
| + | |||
| + | Notes: | ||
| + | |||
| + | - Assert /ACK once per bus transaction for both reads and writes after data address selection is complete. | ||
| + | - Assert /RdCEn once per data word in read burst. First assertion of /RdCEn is coincident with /Ack. Subsequent assertions of /RdCEn are timed using a (usually) shorter wait-state count than the initial access. | ||
| + | |||
| + | ===== Wait-State Generation ===== | ||
| + | |||
| + | * DSA = DSB ⇐ ALE ∥ FB | ||
| + | * CP ⇐ !/SysClk | ||
| + | * /MR ⇐ !(/Rd & /Wr) | ||
| + | * /BusErr ⇐ !Q7 | ||
| + | |||
wiki/nightowl/buscycle.1533836583.txt.gz · Last modified: 2018/08/09 13:43 by gtfjt
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